1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a semiconductor device layout effective for suppressing soft errors.
2. Description of Related Art
Along with recent miniaturization in a semiconductor process of a semiconductor device composed of field effect transistors such as MOSFETs, a transient error (soft error) resulting from radiation (for example, high-energy neutron radiation, thermal neutron radiation, and a radiation) has been recognized as a problem. As an example of the soft error, there is SEU (Single Event Upset) that logic inversion occurs due to charges accumulated in a node decrease due to charges resulting from radiation. In general, the occurrence of the SEU depends on a trade-off between an amount of charges accumulated in an information storage node (node voltage*node capacitance) and an amount of charges gathered to the information storage node (collected charge amount) out of the charges generated in a substrate due to radiation. The collected charge amount is generally proportional to an area (volume, to be exact) of the information storage node. As a result of experiments made by the inventors of the present invention, it is revealed that a smaller diffusion layer has a higher resistance to the SEU as long as a voltage level is constant. If a voltage decreases due to miniaturization, the decreasing rate is determined depending on a relation between the accumulated charge amount and the collected charge amount as mentioned above.
The SEU causes a problem of, for example, data inversion that data stored in a memory cell is different from the original data. To give a typical countermeasure against the SEU, a capacitor is added to the storage node or an ECC (Error Correction Code) is added to a circuit.
The memory cell can avoid the SEU by taking the above countermeasure. However, if this countermeasure is adopted against a SEU that occurs in a circuit transmitting a clock signal or the like, an operational speed is reduced or a chip area is considerably increased, so this countermeasure is inappropriate.
In contrast to the SEU (data inversion) of the memory cell, SET (Single Event Transient) is a signal transmission error resulting from a noise generated by radiation being emitted to a signal transmitting logic circuit (hereinafter referred to as “dynamic circuit” for convenience sake).
Regarding the SET, it is reported by Norbert Seifert, et al. in “Frequency Dependent of Soft Error Rates for Sub-micron CMOS Technologies” that the SEU is more likely to occur in a circuit having more signal paths and higher operational frequency. This relation can be expressed as model expressions, Expressions 1 and 2:Pset∝f(f=operational frequency)   (1)Pset∝N(N=target signal path)   (2)where Pset represents an error occurrence rate.
That is, as an operational frequency of a semiconductor integrated circuit improves, the occurrence of the SET increases as understood from Expression 1. As miniaturization in the semiconductor process proceeds and a circuit is upsized, the occurrence of the SET increases as understood from Expression 2.
As a countermeasure against the SET, a technique of preventing the SET using a majority circuit or a coincidence circuit is described in Pitsini Mongkolkachit et al., “Design Technique for Mitigation of Alpha-Particle-Induced Single-Event Transients in Combinational Logic”. However, incorporating the majority circuit or coincidence circuit increases a circuit area, so there is a possibility that necessary functional parts cannot be embedded in a limited area.
In general, most blocks of the semiconductor integrated circuit have an active mode and a suspend mode. The SET is an error that occurs in the active mode. As understood from the above explanation, parts that are operating at high speeds all the time most need the measure for the SET. Examples of the parts include a ring oscillator circuit for generating an internal clock of the semiconductor integrated circuit. FIG. 7 shows an example of a conventional typical ring oscillator circuit.
In the ring oscillator circuit of FIG. 7, an odd number of inverter circuits are connected in series, and an output of the last inverter circuit is an input of the first inverter circuit. FIG. 8 shows a layout example of two of inverter circuits that constitute the ring oscillator circuit.
As shown in FIG. 8, in the inverter circuits, a PMOS transistor is arranged on the power supply potential VCC line side, and an NMOS transistor is arranged on the ground potential GND line side. A gate electrode G is shared between the PMOS transistor and the NMOS transistor. Source regions S of the PMOS transistor and the NMOS transistor are formed adjacent to one side of the gate electrode G, and drain regions D of the PMOS transistor and the NMOS transistor are formed adjacent to the other side of the gate electrode. Further, the source region S of the PMOS transistor is connected with a power supply potential VCC, and the source region S of the NMOS transistor is connected with a ground potential GND. Moreover, the drain regions D of the PMOS transistor and the NMOS transistor are connected with each other, and an interconnection therebetween is an output of each inverter circuit. Components of the ring oscillator circuit are laid out such that the inverter circuits are connected in series.
FIG. 9 shows another layout example of the inverter circuit. The inverter circuit of FIG. 9 is different from that of FIG. 8 in that a common source region S is used in place of the two source regions S of the two inverter circuit of FIG. 8 to thereby reduce a layout area.
However, if radiation is applied to an output of the inverter circuit with the ring oscillator circuit layout of FIGS. 8 and 9, a logic type of an output is inverted and a phase of a generated clock is shifted, which causes the SET in some cases. The clock phase shift leads to a problem in that a synchronizing circuit using the clock causes a malfunction. This logic inversion is described in detail below.
FIG. 10 is a sectional view taken along the line A-A′ of the inverter circuit of FIG. 8 in the case of applying the radiation to a drain of the NMOS transistor. The NMOS transistor has a source S, a gate G, and a drain D, and a depletion layer E is formed around the source and the drain. When the radiation is applied to the drain of the NMOS transistor, a pair of hole and electron is generated in orbit. At this time, the depletion layer seems enlarged due to an electric field generated by the pair of hole and electron. This area is called a “funneling area F”.
As shown in FIG. 11, in the depletion layer E and the funneling area F, holes and electrons move due to drift or diffusion. Thus, when electrons gather in the drain D, the electrons are accumulated in the drain D of the NMOS transistor. As a result, even if the output of the inverter circuit is at High level (for example, power supply potential), the output potential of the inverter circuit decreases to Low level (for example, ground potential) in some cases.
As a solution to the above problem, Japanese Unexamined Patent Application Publication No. 2003-273709 discloses a technique of avoiding the inversion of an output of a flip-flop or the like. However, a circuit disclosed in Japanese Unexamined Patent Application Publication No. 2003-273709 is intended to prevent the inversion of stored data by adding an element to an output stage. Thus, there is a problem in that this circuit cannot be applied to a circuit that operates all the time like the ring oscillator circuit.